---
license: apache-2.0
base_model:
- timm/convmixer_768_32.in1k
pipeline_tag: image-classification
tags:
- image-classification
- computer-vision
- renesas
- x5h
- onnx
- convmixer
---

# ConvMixer-768/32 (ONNX) – Renesas X5H

## Introduction

This repository hosts **ConvMixer-768/32**, targeting the **Renesas R-Car X5H** platform for
image classification inference on the NPX6 NPU.

- **Model Architecture:** ConvMixer — a "patches are all you need" architecture that applies
  a ViT-style patch embedding followed by repeated depthwise+pointwise convolution mixer
  blocks (no attention or MLP-mixer); this checkpoint uses hidden dimension 768 and depth 32
- **Source Model:** [timm/convmixer_768_32.in1k](https://huggingface.co/timm/convmixer_768_32.in1k)
  — original checkpoint from the paper authors, [locuslab/convmixer](https://github.com/locuslab/convmixer)
- **Task:** Image Classification (ImageNet-1k, 1000 classes)
- **Parameters:** 21.1M (timm model card: Params (M): 21.1, GMACs: 19.5; paper reports ~21M
  params, 80.2% top-1 on ImageNet for this exact configuration)
- **Paper:** "Patches Are All You Need?" (Trockman & Kolter, 2022,
  [arXiv:2201.09792](https://arxiv.org/abs/2201.09792))

## Deployment Flow

The FP32 ONNX model is auto-cast to **INT8** by the Renesas MWMX toolchain at compile time — no
separate quantization step is required.

```
convmixer_768_32_..._optimized.onnx (FP32)
        │
        └─▶  MWMX Runtime  ──▶  INT8 auto-cast  ──▶  NPX6 NPU
```

## Provided Artifacts

| Artifact | Status | Notes |
|----------|--------|-------|
| **FP32 (ONNX)** | ✅ Published | `fp32/convmixer_768_32.onnx` — auto-cast to INT8 by the MWMX toolchain at compile time (see Deployment Flow above); no separate INT8 file is shipped |

## Performance

Measured on **Renesas R-Car X5H** via the MWMX runtime (APM50 ship-performance CI pipeline).

> **Benchmark configuration:** Single NPU · Single AI Core · Batch size: 1 · Input: 3 × 224 × 224

| Runtime      | Precision    | Device                             | Latency (ms) | Type     |
| :----------: | :----------: | :---------------------------------: | :----------: | :------: |
| MWMX Runtime | INT8 (auto)  | X5H · 1× NPU · 1 Core · 850 MHz     |   16.503918  | Measured |

> This is among the higher-latency classifiers in this benchmark sweep, consistent with
> ConvMixer's relatively heavy patch-embedding + deep-mixer design (19.5 GMACs) compared to
> mobile-oriented CNNs of similar parameter count. Only the 1-AI-core slice was run in the
> source benchmark export — the 12-core slice was skipped, so no 12-core row is reported here.

### Accuracy

TBD — not yet measured/published for this repo.

---

## Runtime Details

### MWMX Runtime

- **Engine:** Renesas MWMX (Middleware MX) native inference runtime
- **Input format:** FP32 ONNX (compiled by the MWMX toolchain)
- **NPU execution precision:** INT8 (auto-cast by MWMX toolchain)
- **Execution target:** NPX6-48K NPU on R-Car X5H

---

## Prerequisites

To run inference on Renesas R-Car X5H, you need:

1. **Renesas R-Car X5H board** with NPX6 NPU
2. **Renesas MWMX Runtime**
3. **Hugging Face CLI** to download the model

## Download

```bash
hf download Renesas/ConvMixer-768-32-ONNX --repo-type=model --include "fp32/*"
```

---

## Benchmark Methodology

- **HIL runs:** Hardware-in-the-loop — measured on physical R-Car X5H silicon via the MWMX
  runtime (`metawaremx_runtime` CI pipeline, "APM50" ship-performance target)
- **Precision:** FP32 ONNX input; INT8 execution (auto-cast by MWMX)
- **Slices:** only the 1 AI core slice was run for this model; the 12-core slice was skipped
  in the source export