And here we’ve been complaining about Flat Pack No-Lead chips when this guy is prototyping with Ball Grid Array in a Wafer-Level Chip Scale Package (WLCSP). Haven’t heard that acronym before? Neither had we. It means you get the silicon wafer without a plastic housing in order to save space in your design. Want to use that on a breadboard. You’re crazy!
Eh, that’s just a knee jerk reaction. The wafer-level isn’t that unorthodox as far as manufacturing goes. It’s something like chip on board electronics which have that black blob of epoxy sealing them after the connections are made. This image shows those connections which use magnet wire on a DIP breakout board. [Jason] used epoxy to glue the wafer down before grabbing his iron. It took 90 minutes to solder the nine connections, but his second attempt cut that process down to just 20. After a round of testing he used more epoxy to completely encase the chip and wires.
It works for parts with low pin-counts. But add one row/column and you’re talking about making sixteen perfect connections instead of just nine.