The challenge to produce higher density chips requires a change in the decade-old system design flow. We are at an inflection point similar to the move from schematic-based to hardware description language (HDL)-based design. Three major problems need to be addressed to enable engineers to design and implement the multi-million gate chips forecast by Moore's Law:
- Large volume of design detail demands a higher level of design abstraction
- Improved simulation performance and debugging are critical
- Software/hardware integration and verification must start earlier
The EDA industry has tried to address these issues with extensions to existing languages (Verilog 2001, SystemVerilog) and introducing verification specific languages (Vera, e) with some incremental success or at least hope of success.
But, incremental changes to these languages and tools do not offer an encompassing solution to the problem at hand. Plus, changes in some cases can obscure the power of the existing products to meet the needs they address. Verilog is a well-established register transfer level (RTL) language for simulation and synthesis. Does a Verilog that includes mailboxes and semaphores really add value to RTL synthesis?
What is needed is a language that is based on an object-oriented foundation, provides fast simulation performance and can easily be used for hardware/software integration. SystemC, the library extension to C++, provides all three answers.
SystemC is a naturally object-oriented language that allows designers to use familiar hardware concepts such as modules and interfaces to model their design at high and intermediate levels of abstraction. Since SystemC is C++, simulation performance is fast. The high abstraction modeling and increased performance enables the creation of software development platforms much sooner in the design process, allowing software integration and testing at the earliest possible point. This all adds up to greater parallel development efforts resulting in earlier time-to-market and increased quality of the final product.
The issue with SystemC is not whether it is technically able to meet the needs of next-generation designs, but how to harness its power and produce a methodology with the right tools to enable a SystemC design flow. The SystemC language is free and can be downloaded from the Open SystemC Initiative web site.
But, the language is just the starting point. C++ is a powerful language and SystemC class libraries add hardware design-specific modeling constructs that increase the power of the language to meet the needs of next generation hardware design. The EDA industry must now provide a complete design flow that includes synthesis, translation, debugging and checking tools to allow the designer to fully use the power of SystemC for hardware design.
There are two possible SystemC design flows -- either a single language flow using SystemC from architecture all the way to gates, or a mixed-language flow using SystemC down to RTL synthesis and then using an existing HDL for design implementation. Although some speak of a single language flow as the Holy Grail of EDA, there is no inherent reason why a single language flow is better. Let us learn from software and firmware design where C/C++ and assembly languages happily coexist.
If the EDA industry were to focus on developing front-end, high-abstraction level SystemC tools, we can then continue to use languages like Verilog where they have the most power -- as gate-level implementation languages. The mixed-language SystemC flow is both technically and business-wise a great fit to the design issues we need to solve.
Today many companies are adopting SystemC and implementing their complex systems at a higher level of abstraction. The EDA industry could further promote adoption by continuing to develop tools and design methodologies to support SystemC and truly harness its power and flexibility.
Joan Bartlett is president of EDA startup Actis Design.