Reconfigurable computing allows a lower power consumption to achieve higher performance than software, while maintaining a higher level of flexibility than hardware. Reconfigurable devices, such as field-programmable gate arrays (FPGAs), contain an array of computational elements whose functionality is determined through multiple programmable configuration bits. The hardware can be re-programmed to implement an entirely different circuit.
The focus of the research project ERA (Embedded Reconfigurable Architectures) is to investigate and propose new methodologies in both tools and hardware design to break through the walls of rising pressure in the demand for performance at the lowest possible power budget, and help design the next-generation embedded systems platforms.
In the talk we discuss the proposed strategy to utilize adaptive hardware to provide the highest possible performance with limited power budgets. The envisioned adaptive platform employs a structured design approach that allows integration of varying computing elements, networking elements, and memory elements. For computing elements, ERA utilizes a mixture of commercially available off-the-shelf processor cores, industry-owned IP cores, and application-specific cores. These are dynamically adapted regarding their composition, organization, and even instruction-set architectures, to provide the best possible performance/power trade-offs.
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