Meaning Behind Ram RAS and CAS
RAM is organized into rows and columns, and is accessed
by electrical signals called strobes, which are sent along rows to the columns; when
data is needed, the CPU activates the RAS (Row Access Strobe) line to specify
the row where data is to be found (high bits), then, after a short time, the
CAS, or Column Access Strobe, to specify the column (low bits). After
that, the data goes to the output line and to its destination on the next clock
tick. In other words, the Column Address Strobe dictates how many clocks
the memory waits before sending data on. All registers should be full, or
errors will result, which means a longer wait to make sure, and slower operation.
The shorter the cycle length, the faster the machine runs, at the expense
of stability and data.
Linked with CAS are RAS and RAS-to-CAS, usually set to 2 or 3 with SDRAM
Cycle Length, although you may be able to set them independently, and preferably in the reverse order to the above. Numbers on the chip looking
like 3-2-2 refer to CAS, RAS-to-CAS and RAS, respectively. Running the
chips at higher than rated speeds will mean dropping a CAS/RAS level.
Anyhow, with PC100 SDRAM, the first transfer takes about 50 ns, and the
remaining three inside one cycle, assuming burst mode is active and they
are in the same column. If not, the extra time is determined by CAS Latency,
or the ratio between column access time and clock cycle time, derived from
dividing the former by the clock frequency, and rounding up to the next whole number.
To get the maximum theoretical speed of any memory, divide 1000 by the
access time. For example, 7ns = 1000/7 = 143 MHz. The combination of RAS and CAS specifies a particular RAM location in a
particular RAM chip, where they intersect. Unfortunately, a lot of time is
taken up with transferring these values rather than data. Rather than have
separate pins providing power and data for both, each pin does double
duty, serving rows or columns according to whether the RAS or the CAS pin is
being asserted (that is, receiving current).
Your system will operate most efficiently when the RAS and CAS timings are optimized, but you lose
stability as speed is gained. With page mode, any column of DRAMs in a row
can be accessed any number of times within a short period; since the row
is already specified, only the CAS needs to be applied on subsequent memory
accesses, making things quicker.
RAS and CAS are measured in nanoseconds; the lower the value, the faster
the RAM can be accessed, so the T state delay is similar to wait states. The
RAS access time is actually the speed rating marked on the chip; CAS access
time is around 50% less. Generally, choose the same speed for DRAM reading and
writing, with as few wait states as possible. Burst cycles work the same
way as they do for SRAM, consisting of four figures, with the first being
larger because that's where the address is read; the remaining figures indicate
the clock cycles for the reading of data. They might look like this on the
The first set would be for EDO and the second for Fast Page Mode RAM. The
430HX chipset can use lower figures than the VX. The idea is to keep the figures as low as possible, consistent with your machine working properly.
Note that EDO is only faster when being read from; writes take place at
the same speed as FPM RAM.
This is an article from Phil
Croucher, author of "The
BIOS Companion" Phil has a way of explaining in "plain"
English. The information is well presented and is well above A+ standard.