Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control and gates array data to the output pins. WE# should
remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the device data outputs. The device remains enabled for
read access until the command register contents are altered.
See Reading Array Data on page 25 for more information. Refer to the AC Read Operations on page 40 for
timing specifications and to Figure 17.1 on page 40 for the timing diagram. ICC1 in DC Characteristics
on page 37 represents the active current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines whether the device accepts program data in bytes or
words. See Word/Byte Configuration on page 14 for more information.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. Word/
Byte Program Command Sequence on page 26 has details on programming data to the device using both
standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 7.2 on page 17 and
Table 7.3 on page 18 indicate the address space that each sector occupies. A “sector address” consists of
the address bits required to uniquely select a sector. The Command Definitions on page 25 has details on
erasing a sector or the entire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to Autoselect Mode on page 19 and
Autoselect Command Sequence on page 25 for more information.
ICC2 in DC Characteristics on page 37 represents the active current specification for the write mode. AC
Characteristics on page 40 contains timing specification tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may check the status of the operation by reading the
status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to Write
Operation Status on page 31 for more information, and to AC Characteristics on page 40 for timing diagrams.
February 27, 2009 S29AL016D_00_A8