Effect of Jitter on Data Converters
Sponsor: Synopsys, Inc.
April 24, 2012 -- Clock jitter is probably the most obscure specification in data converters. Clock jitter creates uncertainty around the moment when an analog-to-digital converter (ADC) samples the signal. It also adds to conversion noise, and the combination reduces overall system performance. As data converters have evolved to ever-higher sampling frequencies and higher resolutions, they become more sensitive to external conditions, including clock timing quality. Therefore, clocks must be treated as delicate analog signals requiring minimal disturbances.
This webinar will focus on:
Understanding frequency domain mechanisms that relate jitter to sampling errors enables designers to handle the design trade-offs and to achieve optimal system and data converter performance.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.