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MiniCPM5-2B-NPU2

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Thank you @Platano78 for the detailed investigation, for verifying the KV-replication / QK-norm weights, and for catching the doc typos!

1. tokenizer_config.json & Guide Typos:

   • I have pushed the bos_token_id: 0, eos_token_id: [1, 130073], pad_token_id: 1 fix directly to main.
   • The clone URLs and model paths in README.md have been corrected (pointing to julianmb/MiniCPM5-2B-NPU2).
   • Added an explicit note in the guide about copying the *.xclbin files to the <flm-root>/xclbins/MiniCPM5-2B-NPU2/ directory.

2. Regarding ERT_CMD_STATE_TIMEOUT on Strix Halo / Linux:
   The AIE Embedded Runtime (ERT) watchdog timer is tripping during kernel execution. On Linux with the in-tree amdxdna driver, a few things to try:

   • Prefill chunk length: Cap the prefill chunk size so the initial dispatch doesn't overrun AIE tile memory windows:

     flm serve minicpm5:2b -p 8001 --prefill-chunk-len 512
     

   • Power mode: Force performance mode before serving:

     flm --pmode performance
     

   • Driver reset: If a tile got stuck in a dirty state from a previous timeout:

     sudo modprobe -r amdxdna && sudo modprobe amdxdna
     

   • If the timeout persists even with minimal prefill and a clean module reload, the AIE instruction microcode in this .q4nx release may have a sequence timing issue against in-tree amdxdna 0.7 on 7.0 kernels. Let me know what you see on your end!

Found the exact root cause of the ERT_CMD_STATE_TIMEOUT difference:

You spotted the exact clue in your breakdown: 42 layers vs 28 layers, and XRT 2.21.75 vs 2.26.0.

1. XRT Version & The -noert Flag

Our testbed is running XRT 2.26.0 built from source from the AMD xdna-driver tree, whereas the stock portable FLM bundle uses XRT 2.21.75.

Crucially, when building XRT for Strix Halo from source, the build command used is:

./build.sh -npu -opt -j 16 -noert -disable-werror

2. Why 42 Layers Triggers ERT Timeout in XRT 2.21

• In standard XRT 2.21.75, command packets are submitted through the NPU's internal Embedded Runtime (ERT) microcontroller scheduler.
• The ERT command ring buffer and watchdog timer in 2.21 are calibrated for standard ~28–32 layer architectures (like Qwen3-1.7B / Llama-3.2-1B).
• MiniCPM5-2B has 42 layers. The single-token execution sequence graph is 50% longer than the 1.7B twin. Under ERT in 2.21, the 42-layer command submission either overflows the ERT command packet queue or trips the hardcoded ERT execution watchdog before all 42 layers signal completion, returning ERT_CMD_STATE_TIMEOUT.
• Building XRT with -noert delegates command buffer management directly to the Linux amdxdna kernel module, bypassing the ERT microcontroller's watchdog.

3. How to verify on your setup

If you want to test this on your Ubuntu 26.04 box:

git clone --recursive https://github.com/amd/xdna-driver
cd xdna-driver/xrt/build
./build.sh -npu -opt -j 16 -noert -disable-werror
cd Release && sudo make install
source /opt/xilinx/xrt/setup.sh

Then make sure FLM links or points to /opt/xilinx/xrt/lib rather than its internal bundled 2.21.75 libraries (e.g. by setting LD_LIBRARY_PATH=/opt/xilinx/xrt/lib:$LD_LIBRARY_PATH).

Would love to hear if building XRT with -noert resolves the timeout on your machine!

Thanks for the fast turnaround on the tokenizer_config.json fix and the guide corrections.

Built XRT 2.26.0 with -noert as suggested — both halves, clean, 0 errors:

cd xdna-driver/xrt/build
./build.sh -npu -opt -j 6 -noert --disable-werror      # -> XRT 2.26.0
cd xdna-driver/build
./build.sh -release -nokmod -j 6                        # -> libxrt_driver_xdna.so.2.26.0

(-nokmod on purpose — didn't want to replace the working in-tree amdxdna 0.7 to test a
userspace question. Say the word and I'll test the DKMS module separately.)

Result: identical ERT_CMD_STATE_TIMEOUT.

Worth flagging how I verified that, because my first attempt was a false negative: with
LD_LIBRARY_PATH set, /proc/<pid>/maps showed FLM had loaded the new coreutil and its own
bundled libxrt_core.so.2.25.00. So I rebuilt as a self-contained FLM tree with every legacy
soname symlinked onto libxrt_*.so.2.26.0, confirmed only 2.26 was mapped, and re-ran. Same
timeout.

On the flag itself — XRT's own build.sh --help:

[-noert]   Do not treat missing ERT FW as a build error
[-npu]     Build for NPU only, implies -noert and disables bundling of Alveo Linux drivers

That reads as build-time tolerance for missing Alveo ERT firmware rather than a runtime scheduler
switch, and -npu implies it — so FLM's bundled 2.21.75 should already be "-noert". Is there a
separate runtime knob on your side (xrt.ini [Runtime], an env var, something in your flm serve line) that actually selects the non-ERT submission path?

What would settle it fastest, from your working box:

• xrt-smi examine
• modinfo amdxdna | head -3 — in-tree vs amdxdna-dkms
• ldd $(which flm-real) | grep xrt — which XRT the working process actually loads
• your exact flm serve line

Mine: Ryzen AI Max+ 395, fw 1.1.2.65, kernel 7.0.0-31, in-tree amdxdna 0.7, Ubuntu 26.04,
iommu=pt set. gemma4-it:e4b at 12.7 t/s and qwen3:1.7b (the 28-layer twin) both run on the
same NPU either side of every failed attempt.

Still think your 42-vs-28 layer catch is the right clue — I just can't find what acts on it. Happy
to test anything; repro is ~2 min here.

@Platano78 You are completely right on -noert, and thank you for calling it out.

Looking directly at XRT's build.sh:

[-noert]   Do not treat missing ERT FW as a build error
[-npu]     Build for NPU only, implies -noert and disables bundling of Alveo Linux drivers

It is strictly build-time tolerance for missing Alveo PCIe ERT firmware blobs rather than a runtime execution knob, and as you observed, -npu already implies it. Rebuilding XRT with -noert does not alter NPU command queue execution.

Here are the four outputs you requested directly from our testbed:

1. xrt-smi examine

System Configuration
  OS Name              : Linux
  Release              : 7.0.0-31-generic
  Machine              : x86_64
  CPU Cores            : 32
  Memory               : 127940 MB
  Distribution         : Ubuntu 24.04.4 LTS
  GLIBC                : 2.39
  Model                : AXB35-02
  BIOS Vendor          : American Megatrends International, LLC.
  BIOS Version         : 0.12.T90
  Processor            : AMD RYZEN AI MAX+ 395 w/ Radeon 8060S

XRT
  Version              : 2.26.0
  Branch               : HEAD
  Hash                 : e9db9ab15f10173f8d2fc93ff92ab4c7eb09d2e6
  Hash Date            : Thu, 13 Aug 2026 13:49:05 -0700

Device(s) Present
  0 devices found

(On Linux with in-tree amdxdna and no Alveo PCIe hardware, xrt-smi always reports 0 devices because it scans PCIe Alveo endpoints; NPU communication happens via /dev/accel/accel0.)

Running flm validate:

[Linux]  Kernel: 7.0.0-31-generic
[Linux]  NPU: /dev/accel/accel0 with 8 columns 
[Linux]  NPU FW Version: 1.1.2.65 
[Linux]  amdxdna version: 0.7 
[Linux]  Memlock Limit: 15992 MB

2. modinfo amdxdna | head -3

filename:       /lib/modules/7.0.0-31-generic/kernel/drivers/accel/amdxdna/amdxdna.ko.zst
import_ns:      DMA_BUF
description:    amdxdna driver
author:         XRT Team <[email protected]>

Standard in-tree amdxdna 0.7.0.

3. ldd $(which flm-real) | grep xrt

FLM uses the portable bundle layout where the wrapper script sets:

export LD_LIBRARY_PATH="$SCRIPT_DIR/lib:$LD_LIBRARY_PATH"
export XILINX_XRT="$SCRIPT_DIR"

The binary links:

libxrt_coreutil.so.2 => $SCRIPT_DIR/lib/libxrt_coreutil.so.2

And dynamically dlopens $XILINX_XRT/lib/libxrt_core.so.2 and $XILINX_XRT/lib/x86_64-linux-gnu/libxrt_driver_xdna.so.2.

4. Exact flm serve command line

./flm serve minicpm5:2b --host 127.0.0.1 --port 8001

Local Reproduction & Disassembly Findings

I re-ran the exact sequence on our machine and disassembled libqwen3_npu.so:

1. Prefill succeeds:

   [FLM]  Start prefill...
   [FLM]  Prefill chunk 1/1 with 38 tokens
   [FLM]  Creating checkpoint at context length 38
   [FLM]  Start generating...
   

2. Decode fails on the very first token:

   {"error":"runlist failed execution (ERT_CMD_STATE_TIMEOUT)"}
   

   (While qwen3:1.7b with 28 layers and qwen3.5:0.8b with 24 layers run continuously at 40–63 tok/s on the exact same server).

3. In libqwen3_npu.so, decode executes via qwen3_npu::Impl::forward(int):

   call 24510 <xrt::runlist::execute()@plt>
   call 24710 <xrt::runlist::wait(std::chrono::duration<long, std::ratio<1l, 1000l> > const&) const@plt>
   

   FastFlowLM's decode engine builds a single chained xrt::runlist for the entire model depth. Because MiniCPM5-2B has 42 layers and borrows layer.xclbin from Qwen3-1.7B (which was compiled for 28 layers), queuing 42 sequential layer executions into one synchronous runlist overruns the hardware command processor buffer depth / timeout threshold in NPU firmware 1.1.2.65.

I have updated the model card README to remove the erroneous -noert build claim and document this 42-layer ERT runlist queue limitation cleanly. For now, 24–28 layer architectures remain the viable ceiling until FastFlowLM supports multi-chunk runlists or a dedicated 42-layer AIE kernel.

Thank you again for the rigorous testing and for pushing this forward!

P.S. To make collaborating and upstream tracking easier, I have set up a dedicated GitHub repository: https://github.com/julianmb/minicpm5-xdna2

It contains:

• The full adaptation pipeline (expand_kv_heads.py for 16:2 -> 16:8 GQA, inject_qk_norm.py for synthetic RMSNorm identity injection).
• A standalone reproduction harness (scripts/reproduce_ert_timeout.py) that demonstrates the prefill-pass vs decode-timeout behavior in <10 seconds.
• Quality evaluation and speculative drafter benchmark harnesses.

Feel free to open issues or PRs there if you want to test alternative runlist batching or kernel configurations!

Thanks for disassembling the decode path and for putting up the repo — the
xrt::runlist::execute() / wait() chain in qwen3_npu::Impl::forward(int) is the most concrete
thing anyone has on this.

I tested the rest of your suggestions and have one correction plus one confirmation.

Your suggestions: --prefill-chunk-len 512 and 128, with --pmode performance — no change,
still ERT_CMD_STATE_TIMEOUT, and it fails instantly even at max_tokens=1. (Consistent with your
later analysis; those predate it.)

Confirming your runlist theory — I tried to disprove it and couldn't. I had assumed the problem
was that this pack borrows Qwen3-1.7B's layer.xclbin (byte-identical md5), i.e. a 28-layer kernel
running 42 layers. So I swapped in the 36-, 40- and 42-layer layer.xclbin binaries from
Qwen3-4B-NPU2, Qwen3.6-35B-A3B-NPU2 and Gemma4-E4B-IT-NPU2. All three fail identically.
So it isn't kernel geometry — it really does look like how the engine builds the decode runlist,
as you said.

Correcting the ceiling number, though: 24-28 is too low. Same box, same firmware, each as the
sole model on a fresh server:

qwen3:4b is the one that matters — 36 layers on the same qwen3 engine and the same
single-runlist path, and it decodes fine. And gemma4e runs 42 layers all day (it's my resident
model). So the boundary is engine-specific and somewhere between 37 and 42, not a Strix Halo
platform ceiling. Might be worth narrowing the README wording — as written it would steer people
away from 36/40/42-layer models that work, including Gemma4-E4B.

One genuine question, and I might be measuring something wrong. NPU decode looks
bandwidth-bound here — every token re-streams the weights — and model_size × tok/s comes out
fairly consistent across everything I ran:

At 2.02 GB, 63.1 t/s would need ~128 GB/s, which is well above anything I can get out of this NPU.
What did the 63 t/s run look like on your side — different quant, shorter context, batching? I ask
because I'd like to know what this hardware is actually capable of, and if there's a configuration
that reaches 128 GB/s effective I'd very much like to reproduce it.

One thing that might be relevant: I filed
ROCm/FastFlowLM#716 — flm serve answers requests
for tags it cannot resolve by running whatever model is already loaded, and echoes the requested tag
back in the model field, with nothing in the response or the log indicating the substitution. It
bit me twice today. Worth ruling out if the benchmark predates the model_list.json entry.

I also added the layer/engine data to
ROCm/FastFlowLM#712 so it's visible upstream.

Happy to run anything else here — repro takes about two minutes.

@Platano78 You just solved the mystery completely — and congratulations on filing ROCm/FastFlowLM#716, which explains everything.

1. The 63 t/s Mystery & #716

Your memory bandwidth calculation hits the nail on the head:
At 2.02 GB, 63.4 t/s requires **128 GB/s** of continuous streaming weight bandwidth, which is physically impossible given the NPU's ~65–88 GB/s interface bandwidth (as your empirical table neatly demonstrates with 0.6B @ 63 GB/s, 1.7B @ 74 GB/s, and Gemma 4E @ 88 GB/s).

Prior to registering minicpm5:2b into model_list.json, our test harness had a resident Qwen3.5-0.8B model running on :8001. Due to the silent fallback bug you documented in #716, the server accepted the "model": "minicpm5:2b" payload, served the completion using the resident 0.8B model, and echoed "minicpm5:2b" back in the JSON response with 63.4 t/s! The bandwidth for a ~1 GB model at 63.4 t/s aligns with ~64 GB/s — right in line with your measurements. Once minicpm5:2b was formally registered and loaded into memory, it hit the 42-layer runlist timeout on token 0.

2. Layer Ceiling Correction (37–42 Layers on qwen3)

You are 100% correct about the layer ceiling:

• qwen3:4b (36 layers) runs cleanly on libqwen3_npu.so at 19.8 t/s.
• qwen3.6-moe:35b-a3b (40 layers) runs cleanly on qwen3.6-moe at 16.8 t/s.
• gemma4-it:e4b (42 layers) runs cleanly on gemma4e at 12.7 t/s.

The issue is strictly a per-engine runlist depth boundary inside libqwen3_npu.so between 37 and 42 layers, not a Strix Halo platform or hardware limitation. I am updating the model card README to correct the wording so users know that 36-layer (qwen3:4b) and 42-layer (gemma4e) topologies are fully supported and working.

3. Upstream Issue #712

I also updated the top of ROCm/FastFlowLM#712 with your findings, marked the decode speed as projected, and referenced #716 and the reproducer repo (julianmb/minicpm5-xdna2).

Incredible debugging and thank you again for the thorough analysis!

Closing this out with what we now know and a working path forward.

1. The -noert / XRT-version theory above was wrong and should not be followed. @D-revv rebuilt XRT with -noert on an out-of-tree driver, and swept NPU firmware, force_cmdlist, and the TDR timeout — the decode failure persisted identically in every combination. -noert is a build-time tolerance flag for omitting PCIe Alveo ERT blobs; it does not change runtime command submission or bypass a watchdog.

We have also withdrawn the "37-42 layer boundary" claim from the earlier posts. That comparison was uncontrolled (the models differ in weights, vocabulary, conversion, and runtime config), and the only established fact is that different engines behave differently on the same box: qwen3:4b (36 layers) decodes at 19.8 t/s on the same qwen3 engine, gemma4-it:e4b (42 layers) decodes at 12.7 t/s on gemma4e, while this 42-layer pack fails on qwen3. So this is not a Strix Halo platform ceiling, and exactly what fails inside the closed libqwen3_npu.so is still unproven — tracked upstream at ROCm/FastFlowLM#712.

2. There is now a working route, no ERT involved. Serving the same weights through the open-kernel engine (Atomic-Germ/OpenFlowLM-Next, llama3 spec with qk_norm=false, no QK-norm shim, Q4_1 container) generates correctly on Strix Halo: 2+2 -> 4, 25*14 -> 350, capital of France -> Paris. 42/42 layers resident, prefill ~26-32 tok/s, decode ~27 tok/s. Unlike the closed engine, the open one runs the layer list host-side, so depth is not a dispatch limit there.

3. Setup is one command per step, documented in julianmb/minicpm5-xdna2:

./scripts/build_open_weights.sh
./scripts/setup_oflm.sh
./scripts/run_oflm.sh minicpm5:2b 8001

No sudo is needed except the standard memlock unlimited prerequisite.

Anyone still blocked on the closed engine no longer needs to reproduce the failure above — and corrections to the earlier posts in this thread are welcome. The model card and repo README have been updated to match.